One common type of integrated circuit driver utilizes two power MOSFET switches in a totem pole (half-bridge) topology. The MOSFET switches are typically NMOS switches that are connected in series. The power MOSFET switches are driven to conduct alternately. One of the MOSFET switches is designated as a high side switch, and the other MOSFET switch is designated as the low side switch. In one application, by selectively switching the power MOSFET switches in an alternating fashion, a load can be driven with an alternating current. In such a manner, a DC to AC inverter is formed. Likewise by controlling the switches according to an input signal (such as an acoustic signal), a class D audio amplifier is formed. Further, the same half bridge topology using a stable DC reference as the input can be used to create a DC power supply.
The gate of the high side switch is typically driven by a bootstrapped power supply. This is done to allow use of an NMOS switch, which has roughly half the on resistance of a PMOS switch of the same area. A bootstrap capacitor is used to increase the voltage available to the gate of the high side switch. FIG. 1 shows a prior art simplified schematic of an integrated circuit driver (IC) used in conjunction with a bootstrap capacitor to drive a load. The IC driver provides current to drive a load. A bootstrap capacitor Cb has one terminal connected to the output of the IC driver. The other terminal of the bootstrap capacitor Cb is provided back to the IC driver to drive the gate of the high side switch.
A more detailed schematic of the IC driver of FIG. 1 is shown in FIG. 2. As seen in FIG. 2, the IC driver 101 includes the high side switch 107 and the low side switch 109. The high side switch 107 is driven by gate drive and fault circuit 111. Similarly, the low side switch 109 is driven by gate drive and fault circuit 113. The gate drive and fault circuits 111 and 113 are operative to control the switching of the high side and low side switches 107 and 109. In addition, the gate drive and fault circuits 111 and 113 typically include fault detection circuitry and a bootstrap supply monitor. These additional functions are generally needed to measure whether there is a fault condition on the switch or whether the bootstrap supply is sufficient for the IC to operate properly.
The precise configuration of the gate drive and fault circuits 111 and 113 may be varied, but generally the configuration and operation is well known in the prior art. Note that the gate drive and fault circuit 113 used to control the low side switch 109 operates using a first supply voltage Vsp1. The low side switch 109 does not require a bootstrapped power supply. In contrast, the gate drive and fault circuit 111 that controls the high side switch 107 is connected to the bootstrap capacitor 103.
The output of the IC driver 101 is taken from the node connecting the high side switch and the low side switch. In physical terms, the output node is a conductive pad on the integrated circuit, designated in FIG. 2 as SWpad 115. The integrated circuit die is then set into a package wherein the pad SWpad 115 is connected to a package pin SWpin 117. The connection between the pad 115 and the package pin 117 is typically made through a bond wire formed of gold, copper, or other highly conductive material.
Nevertheless, the bond wire between the pad 115 and the package pin 117 includes some finite amount of parasitic inductance Lp1 and parasitic resistance Rp1. When current is supplied through the pin 117 to the load 105, invariably there will be a loss of voltage across the parasitic inductance Lp1 and parasitic resistance Rp1.
The amount of the voltage drop is important because any voltage that develops across the bond wire between SW pad and SW pin, subtracts directly and instantaneously from the bootstrap supply. Because of the large value of current and high rate of change of that current in the bondwire, the voltage drop can be significant, on the order of two or more volts. This sudden drop in the internal bootstrap supply voltage will adversely affect any signal processing operating under the internal bootstrap supply, such as the bootstrap supply monitor and fault check circuits.
Therefore, the arrangement shown in FIG. 2 having an imprecise and noisy bootstrap supply is undesirable.